54 lines
1.9 KiB
C
Executable File
54 lines
1.9 KiB
C
Executable File
/* Trapping floating-point exceptions.
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Copyright (C) 2023-2024 Free Software Foundation, Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>. */
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/* HAVE_FPE_TRAPPING
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Defined to 1 when sigfpe_on_invalid is available. */
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/* sigfpe_on_invalid
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Enables a SIGFPE signal when an FE_INVALID exception occurs.
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A SIGFPE signal by default terminates the program.
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Returns >= 0 when successful, -1 upon failure. */
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#include <fenv.h>
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static int
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sigfpe_on_invalid ()
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{
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/* Clear FE_INVALID exceptions from past operations. */
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feclearexcept (FE_INVALID);
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/* An FE_INVALID exception shall trigger a SIGFPE signal.
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This call may fail on arm, arm64, riscv64 CPUs.
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Also, possibly a bug in glibc/sysdeps/m68k/fpu/feenablxcpt.c: it sets
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only bit 13, but should better set bits 15, 14, 13 of the control
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register together. See
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<https://sourceware.org/bugzilla/show_bug.cgi?id=30993>. */
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int ret = feenableexcept (FE_INVALID);
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if (ret == -1)
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return -1;
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return 0;
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}
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/* But it does not work on RISC-V. That's because the fcsr register has only
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bits for floating-point exception status, but no bits for trapping
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floating-point exceptions. */
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/* And it does not work on arm with software floating-point emulation. */
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#if !(defined __riscv || (defined __GLIBC__ && defined __arm__ && defined __SOFTFP__))
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# define HAVE_FPE_TRAPPING 1
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#endif
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